The present invention relates generally to circuitry and techniques for measuring contact resistance of leads or pins of packaged integrated circuits and bonding pads or test pads of un-packaged integrated circuits without using the expensive prior techniques such as use of Kelvin contacts which eliminate errors caused by contact resistances.
Parametric testing of packaged integrated circuit chips involves pressing tips of conductive “contactors” against package leads or pins of packaged integrated circuits. Parametric testing of un-packaged integrated circuit chips can be performed by pressing conductive probes against bonding pad metallization surfaces or test point metallization surfaces. In any case, there always is a parasitic “contact resistance” that occurs due to the making a contact between the contactor surface or the probe tip surface and the package pin or bonding pad surface. The value of the contact resistance usually is unknown and often results in degradation of test signals and reduces testing accuracy. The signal degradation may lead to a need for larger guard bands around the measured parameters. Increased guard bands usually result in lower chip yields, and hence results in higher integrated circuit chip costs.
A common source of measurement error in the testing of integrated circuits is the above mentioned contact resistance. Any package pin or integrated circuit bonding pad that sources or sinks current is subject to voltage drops or voltage increases across the associated contact resistance. It is difficult to control the contact resistance because it is caused by many variables. For example, normal wear on package pins or bonding pads and/or probe interface surfaces, contact surface irregularities, contamination, variations in probe contact surface planarity, and variation in the plunge force applied to the contact probe or contactor surface all can cause significant changes in the contact resistance. Regular probe interface surface maintenance and cleaning usually minimize the magnitude of the contact resistance, but do not necessarily reduce chip-to-chip variation in the values of contact resistance and/or pin-to-pin variation that occur during integrated circuit testing because there are too many causes of contact resistance variation that are not adequately addressed by ordinary maintenance and cleaning procedures.
Contact resistance errors usually limit the accuracy of conventional trimming operations in integrated circuits in which the values of components such as thin film resistors are precisely trimmed by conventional laser trimming techniques or other conventional trimming techniques. The contact resistance errors usually also limit the capabilities of parametric testing of integrated circuits. Contact resistance errors also necessitate the use of wider guard bands for measured parameters, looser integrated circuit product specifications, and lowering of otherwise achievable circuit performance objectives for the integrated circuits.
One known solution to the problem of contact resistance errors is to use Kelvin contacts during parametric testing of packaged or un-packaged integrated circuits. A Kelvin contact utilizes two probe contacts to the bonding pad, in such a manner as to provide a zero-current path to the pad through one probe contact for the purpose of precisely sensing the voltage on the pad and a standard current path through the other probe contact. This technique facilitates accurate measurement of a voltage of each integrated circuit terminal at which a Kelvin contact is provided under all but extreme contact resistance conditions. Unfortunately, Kelvin contacts are expensive because of the two required probes and the required expensive sensing and driving circuitry. Consequently, use of Kelvin contacts is not available or practical for many integrated circuit package options. This means that many integrated circuits must be tested without the accuracy achievable by use of Kelvin contacts and therefore suffer contact resistance errors that reduce both manufacturing yield and integrated circuit performance.
FIG. 1 illustrates a standard single contact per pin arrangement. The Device under Test (DUT) is a packaged integrated circuit which includes three package leads or pins PN1, PN2, and PN3. Pin PN3 is contacted by a “contactor” C3 which is connected to conductors 3 and 4. Contactors are resilient, spring-biased or cantilevered conductive contact surfaces supported in a contact assembly included in a parametric tester/contactor machine such as parametric tester/contactor machine 18A in subsequently described FIG. 3A, and a conventional integrated circuit package handler grips the integrated circuit package 1A and “plunges” its pins PN1,2 . . . etc. against the contactors PRB-1,2 . . . etc. Conductor 3 is connected to the sense output of a force/sense power supply unit 2 which produces a positive supply voltage VCC on pin PN3 relative to a ground voltage on ground conductor 5. Contactor 3 is pressed against pin PN3, resulting in a contact resistance R3 between contactor C3 and pin PN3. Similarly, pin PN2 is contacted by a ground contactor C2 connected to ground conductor 5, producing a contact resistance R2 between ground contactor C2 and pin PN2. Output pin PN1 is contacted by a contactor C1 that is connected to conductor 6 and pressed against pin PN1, producing a contact resistance R1 between it and contactor C1. A load resistor RL is connected between conductor 6 and ground conductor 5. A quiescent current IQ flows through pin PN2 and contact resistance R2 into ground conductor 5. A load current IL flows through pin PN1, contact resistance R1, and load resistance RL. A total current IT flows through contactor C3, contact resistance R3, and pin PN3. High impedance voltmeter 7 has its (+) input connected to conductor 6 and its (−) input connected to ground conductor 5.
The voltage drops across contact resistances R2 and R1 in FIG. 1 affect the parametric measurements, since the actual voltage measurement between conductor 6 and ground conductor 5 is now equal to Vout+((IQ*R2)−(IL*R1)), where IQ is the quiescent current, and IL is the load current. However, the desired measurement is an accurate value of Vout, which is the potential of PN1 relative to the potential of PN2 of the DUT 1. The measurement of the voltage on conductor 6 is an erroneous representation of Vout because of the IL-dependent voltage drop across contact resistance R1, and also because of the IQ-dependent voltage drop across contact resistance R2. This erroneous representation decreases in the accuracy of the measurement of Vout. Consequently, the performance specifications of the DUT may need to be lowered, and guard bands of various tested parameters of the DUT may need to be broadened, reducing the manufacturing yield of the DUT and increasing its cost.
As subsequently explained in more detail, parametric testing measurements using the above mentioned Kelvin contacts require a first circuit path that is a load path or current-conducting path and a second circuit path which is a zero-current path, where zero-current is defined here as being extremely low current (e.g., pico-amperes). A high impedance meter (or high impedance buffer) is utilized so that the actual package pin (or bonding pad) is located ahead of the contact resistance being measured.
FIG. 2 illustrates Kelvin contacts in a typical test application where high precision and high accuracy are required and contact resistance is not controllable. As in FIG. 1, a packaged integrated circuit DUT includes three pins PN1, PN2, and PN3. Pin PN3 is contacted by a conductive probe or “contactor” 3A and an associated conductor 3 which is connected to the very high impedance “sense” input of a power supply 2 that uses voltage feedback via conductor 3 to produce a precise positive supply voltage VCC on pin PN3 relative to a ground voltage on ground conductor 5. Contactor 3A is pressed against pin PN3, resulting in a contact resistance R31 between contactor 3A and pin PN3. Pin PN3 is also contacted by a contactor 3B and associated conductor 4 which is connected to the low impedance “force voltage” output of VCC power supply 2 to produce the precise value of VCC on pin PN3. Contactor 3B presses against pin PN3, resulting in a contact resistance R32 between contactor 3B and pin PN3. Similarly, pin PN2 is contacted by a ground contactor 8A connected to ground conductor 5, producing a contact resistance R21 between ground conductor 5 and pin PN2. Pin PN2 is also contacted by another ground contactor 8B connected to a conductor 5B which is connected to the (−) input of high impedance voltmeter 7, producing a contact resistance R22 between ground conductor 5B and pin PN2. Output pin PN1 is contacted by a contactor 6A electrically connected to conductor 6 is connected to the (+) of voltmeter 7. Contactor 6A is pressed against pin PN1, producing a contact resistance R11 between contactor 6A and pin PN1. A load resistor RL is connected between a contactor 6B and ground conductor SA. Contactor 6B is pressed against pin PN1, producing a contact resistance R12 between contactor 6B and pin PN1.
A quiescent current IQ flows through pin PN2 and contact resistance R21 into ground conductor 5. A load current IL flows through pin PN1, contact resistance R12, and load resistance RL, and a total current IT flows from conductor 4 through contact resistance R32 into pin PN3. High impedance voltmeter 7 has its (+) input connected to conductor 6 and its (−) input connected to ground conductor 5B.
A Kelvin contact measurement is a zero-current technique for measuring the voltage across a device. The method for eliminating the effects of contact resistance using Kelvin contacts in the circuit of FIG. 2 allows measurement of the voltage between package pins PN2 and PN3 without contact resistance errors associated with currents flowing through each of the pins of DUT. Since the input impedance is of voltmeter 7 and of the sense input of power supply 2 are very high, essentially no current flows across contact resistances R22, R11 or R31. There is no voltage drop between pin PN2 and the (−) input of voltmeter 7, no voltage drop between package pin PN1 and the (+) input of voltmeter 7, and no voltage drop across contact resistance R31.
The main prior art technique for obtaining accurate measurements in sensitive to contact resistances of integrated circuit pins and the like requires use of the above-described Kelvin contacts, which are very expensive, and also require use of expensive circuitry for implementing Kelvin contacts.
Most integrated circuits are required to meet rigorous ESD (electrostatic discharge) qualification standards. To meet such standards, inter-pin ESD (electrostatic discharge) diodes are incorporated into most integrated circuits to protect transistors and other devices connected to the pins by the bypassing electrostatic discharge currents around sensitive integrated circuitry. Ordinarily, ESD diodes are provided for each pin of the integrated circuit. Additionally, ESD diodes are ordinarily used during the testing of integrated circuits for checking continuity, i.e., the existence of a continuous electrical path from the tester hardware to the integrated circuit under test. This assures continuity of contact to the test fixture and also ensures integrity of the various wire bonds. This procedure is usually performed prior to applying electrical power to the integrated circuits and prior to the beginning of the parametric testing operation or a trimming operation.
There is an unmet need for a system and method for reducing the effect of inaccuracies caused by contact resistances caused by external probes or contactor surfaces during parametric testing of packaged and/or un-packaged integrated circuits.
There is an unmet need for a system and method for reducing the effect of inaccuracies caused by contact resistances due to external probes or contactor surfaces during parametric testing of packaged and/or un-packaged integrated circuits and that is applicable independently of the integrated circuit package type.
There also is an unmet need for a way to avoid the high cost of using Kelvin contacts during parametric testing of packaged integrated circuits and/or un-packaged integrated circuit chips.